1. Field of the Invention
The present invention relates to a switching regulator, and more particularly to a controlling system where efficiency degradation and an output voltage increase of a DC voltage outputting circuit are small when a light load is imposed.
2. Description of the Related Art
A DC/DC converter as a switching regulator adopts, for example, a bipolar transistor or a MOSFET as a switching means, and controls the duty factor of ON/OFF of the switching means in order to obtain a desired voltage output.
FIG. 1 is a circuit diagram showing a switching controlling circuit for controlling the duty factor of ON/OFF of the above described switching means. An input terminal 1 is input with, for example, an output voltage of a DC voltage outputting circuit. A voltage "Vfb" into which the above described output voltage is divided with dividing resistors R1 and R2 is input to one of input terminals of an amplifier 2. To the other of the input terminals of the amplifier 2, a reference voltage "Vref" is input. The amplifier 2 outputs the control voltage based on both of the inputs to an inversion input "-" of a comparator 3. The comparator 3 compares the voltage between both ends of a sense resistor, which is input to a non-inversion input terminal "+", with the above described control voltage, and generate a reset signal. Note that the voltage between both ends of the sense resistor is a voltage across a current detection sense resistor arranged, for example, in a DC/DC converter shown in FIG. 3.
When a heavy load is imposed, the voltage between both ends of the sense resistor is higher than a peak current setting voltage for a light load, and a comparator 7 outputs a high level signal. Accordingly, the reset signal output from the comparator 3 is input to a reset terminal "R" of a flip-flop circuit 6 via an AND gate 4 and an OR gate 5. Also the reset signal output from a reset pulse generating circuit 10 at predetermined intervals is input to the reset terminal "R" of the flip-flop circuit 6 via the OR gate.
When a light load is imposed, the comparator 7 outputs a low level signal until the voltage between both ends of the same resistor exceeds the peak current setting voltage for a light load. Therefore, the reset signal output from the comparator 3 is not input to the reset terminal "R" of the flip-flop circuit 6. However, the reset signal output from the reset pulse generating circuit 10 at predetermined intervals is input via the OR gate 5. Once the reset signal is input to the reset terminal "R" of the flip-flop circuit 6, the output terminal "Q" of the flip-flop circuit 6 outputs a low level signal, which is inverted by an inverter 11 and input to one of the terminals of the AND gate 9. Therefore, the reset signal of the comparator 3 remains to be input to the reset terminal "R" of the flip-flop circuit 6 via the AND gate 9 and the OR gate 5 until the reset signal of the comparator 3 is cancelled.
FIGS. 2A through 2E are timing charts for explaining the waveforms of the respective components of the switching controlling circuit in the above described state. FIG. 2A indicates the voltage between both ends of the sense resistor, the control voltage, and the peak current setting value respectively by a solid line, a dotted line, and a line-two dash-line. FIG. 2B indicates a set pulse signal to be input to the set terminal "S" of the flip-flop circuit 6; FIG. 2C indicates the output timing of the reset signal to be output from the reset pulse generating circuit 10; FIG. 2D indicates the reset signal to be input to the reset terminal "R" of the flip-flop circuit 6; and FIG. 2E indicates the output (of the output terminal?) "Q" of the flip-flop circuit 6.
As described above, this switching controlling circuit controls the duty factor of the output signal of the output (terminal?) "Q" of the flip-flop circuit 6 by using the reset signal to be input to the reset terminal "R" of the flip-flop circuit 6. The reset signal is generated by making a comparison between the voltage between both ends of the same resistor and the control voltage which is the output of the amplifier 2.
When a heavy load is imposed, the voltage between both ends of the sense resistor is controlled in order to be equal to the control voltage. However, when a light load is imposed, the comparator 7 makes a comparison between the peak current setting voltage for a light load and the voltage between both ends of the sense resistor in order to reduce the number of times that the switching means is turned off for preventing the efficiency from decreasing. The comparator 7 raises the voltage between both ends of the sense resistor up to the peak current setting voltage for a light load by turning on the switching means once. Therefore, the control voltage drops, which leads to further rising of the output voltage of the DC output circuit. As a result, the load regulation which is the fluctuation of the output voltage of the DC voltage outputting circuit due to light and heavy loads, is degraded with the conventional controlling system which prevents the efficiency from decreasing.